1. Field of the Invention
The present invention relates to an organic electroluminescent display device and a method of fabricating an organic electroluminescent display device, and more particularly, to an active matrix organic electroluminescent display device and a method of fabricating an active matrix organic electroluminescent display device.
2. Discussion of the Related Art
Among flat panel displays, liquid crystal display (LCD) devices have been commonly used due to their thin profile, light weight, and low power consumption. However, the LCD devices are not self-luminescent and suffer from low brightness, low contrast ratio, narrow viewing angle, and large overall size.
Organic electroluminescent display (OELD) devices have wide viewing angles and excellent contrast ratios because of their self-luminescence. In addition, since the OELD devices do not require additional light sources, such as a backlight, the OELD devices have relatively small size, are light weight, and have low power consumption, as compared the LCD devices. Furthermore, the OELD devices can be driven by low voltage direct current (DC) and have short microsecond response times. Since the OELD devices are solid phase devices, the OELD devices sufficiently withstand external impacts and have greater operational temperature ranges. In addition, the OELD devices may be manufactured at low cost since only deposition and encapsulation apparatus are necessary for manufacturing the OELD devices, thereby simplifying manufacturing processes.
The OELD devices may be categorized as passive matrix-type OELD devices and active matrix-type OELD devices depending upon a method of driving the devices. The passive matrix-type OELD devices are commonly used due to their simplicity and ease of fabrication. However, the passive matrix-type OELD devices have scanning lines and signal lines that perpendicularly cross each other in a matrix configuration. Since a scanning voltage is sequentially supplied to the scanning lines to operate each pixel, an instantaneous brightness of each pixel during a selection period should reach a value resulting from multiplying an average brightness by the number of the scanning lines to obtain a required average brightness. Accordingly, as the number of the scanning lines increases, the applied voltage and current also increase. Thus, the passive matrix-type OELD devices are not adequate for high resolution display and large-sized areas since the device easily deteriorates during use, and power consumption is high.
Since the passive matrix-type OELD devices have many disadvantages with regard to image resolution, power consumption, and operational lifetime, the active matrix-type OELD device have been developed to produce high resolution images in large display area displays. In the active matrix-type OELD devices, thin film transistors (TFTs) are disposed at each sub-pixel for use as a switching element to turn each sub-pixel ON and OFF. A first electrode connected to the TFT is turned ON/OFF by the sub-pixel, and a second electrode facing the first electrode functions as a common electrode. In addition, a voltage supplied to the pixel is stored in a storage capacitor, thereby maintaining the voltage and driving the device until a voltage of next frame is supplied, regardless of the number of the scanning lines. As a result, since an equivalent brightness is obtained with a low applied current, an active matrix-type OELD device has low power consumption and high image resolution over a large area.
FIG. 1 is a schematic circuit diagram of a pixel structure of an active matrix-type OELD device according to the related art. In FIG. 1, a scanning line 1 is arranged along a first direction, and a signal line 2 and a power line 3 that are spaced apart from each other are arranged along a second direction perpendicular to the first direction. The signal line 2 and the power line 3 cross the scanning line 1, thereby defining a pixel area. A switching thin film transistor (TFT) TS, i.e., an addressing element, is connected to the scanning line 1 and the signal line 2, and a storage capacitor CST is connected to the switching TFT TS and the power line 3. A driving thin film transistor (TFT) TD, i.e., a current source element, is connected to the storage capacitor CST and the power line 3, and an organic electrolumninescent (EL) diode DEL is connected to the driving TFT TD. When a forward current is supplied to the organic EL diode DEL, an electron and a hole are recombined to generate an electron-hole pair through the P(positive)-N(negative) junction between an anode, which provides the hole, and a cathode, which provides the electron. Since the electron-hole pair has an energy that is lower than the separated electron and hole, an energy difference exists between the recombination and the separated electron-hole pair, whereby light is emitted due to the energy difference.
In FIG. 1, when a scanning signal is supplied to the corresponding scanning line 1, the switching TFT TS is turned ON, and a data signal from the signal line 2 is supplied to the driving TFT TD. Then, the driving TFT TD is turned ON, and current from the power line 3 flows to the organic EL diode DEL after passing through the driving TFT TD. Thus, light is emitted from the organic EL diode DEL.
Since an ON ratio of the driving TFT TD depends on a value of the data signal, gray scales can be displayed by controlling the current flowing through the driving TFT TD. In addition, although the data signal is not supplied, the organic EL diode DEL emits light due to data stored in the storage capacitor CST until the next data signal is supplied.
FIG. 2 is a cross sectional view of an active matrix-type OELD device according to the related art. In FIG. 2, a buffer layer 12 is formed on a substrate 10, which includes a light emitting region E for forming images. A thin film transistor T, which may be the driving thin film transistor, is formed on the buffer layer 12. An organic EL diode DEL is formed in the light emitting region E and is connected to the thin film transistor T, and a storage capacitor CST is formed to be connected to the thin film transistor T.
In FIG. 2, a semiconductor layer 14 and a first capacitor electrode 16, which are spaced apart, are formed on the buffer layer 12, and a gate insulating layer 18 and a gate electrode 20 are subsequently formed on a central portion of the semiconductor layer 14. Then, a first interlayer 22 is formed on an entire surface of the substrate 10 to cover the gate electrode 20 and the first capacitor electrode 16. Next, a second capacitor electrode 24 is formed on the first interlayer 22 corresponding to the first capacitor electrode 16, wherein the second capacitor electrode 24 branches off from a power line (not shown). Then, a second interlayer 26 is formed on an entire surface of the substrate 10 including the second capacitor electrode 24.
The semiconductor layer 14 is composed of an active region A, which corresponds to the gate insulating layer 18 and the gate electrode 20, and source and drain regions S and D, which are disposed at both sides of the active region A, respectively. A first contact hole 28 and a second contact hole 30 are formed through the first interlayer 22 and the second interlayer 26 to expose the source region S and the drain region D of the semiconductor layer 14, respectively. In addition, a third contact hole 32 is formed only through the second interlayer 26 to expose the second capacitor electrode 24.
A source electrode 34 and a drain electrode 36 are formed on the second interlayer 26, spaced apart from each other. Accordingly, the source electrode 34 is connected to both the source region S of the semiconductor layer 14 through the first contact hole 28 and the second capacitor electrode 24 through the third contact hole 32, and the drain electrode 36 is connected to the drain region D of the semiconductor layer 14 through the second contact hole 30.
A first passivation layer 40 is formed on an entire surface of the substrate 10 including the source electrode 34 and the drain electrode 36, wherein the first passivation layer 40 has a fourth contact hole 38 exposing the drain electrode 36. A first electrode 42 is formed in the light emitting region E on the first passivation layer 40, and is connected to the drain electrode 36 through the fourth contact hole 38. Although not shown, the first electrode 42 is patterned in each sub pixel area, which is a minimum unit for forming an image.
A second passivation layer 46 is formed on the first electrode 42, and the second passivation layer 46 has an opening 44 exposing the first electrode 42. Accordingly, it is difficult to form the first electrode 42 having a uniform thickness due to step coverage characteristics of the layers under the first electrode 42. Thus, an electric field is concentrated on edges of the first electrode 42, whereby leakage current may be generated. To prevent the leakage current, the second passivation layer 46 covers the edges of the first electrode 42. Then, an organic electroluminescent layer 48 is formed on the second passivation layer 46 in the light emitting region E, and a second electrode 50 is formed on an entire surface of the substrate 10 including the organic electroluminescent layer 48.
The first passivation layer 40 insulates the first electrode 42 from the layers under the first electrode 42, and prevents damage of the under layers since the first passivation layer 40 may be made of an inorganic material, such as silicon oxide (SiO2) and silicon nitride (SiNx), or an organic material, such as an acrylic resin. In addition, the second passivation layer 46 may have a bank shape in order to prevent leakage current and an electrical short due to step coverages in the peripheral portion of the first electrode 42, and in order to reduce parasitic capacitances between the second electrode 50 and a gate line (not shown), i.e., the scanning line of FIG. 1, and between the second electrode 50 and a data line (not shown), i.e., the signal line of FIG. 1.
Additionally, if the first passivation layer 40 is made of an inorganic material, such as silicon oxide and silicon nitride, the first passivation layer 40 is deposited along the shape of the second interlayer 26, and surface roughness of the first passivation layer 40 increases. Thus, characteristics of the first electrode 42 on the first passivation 40 are lowered. In addition, the first electrode 42 is formed by a plasma enhanced chemical vapor deposition (PECVD) method, which deposits a thin film by decomposing reaction gas molecules by collision with electrons having high energy in plasma and sticking decomposed gas atoms to the surface of a substrate, or by a sputtering method, which deposits a thin film by colliding ions of high energy against a target of a solid phase and detaching atoms and molecules from the target. Thus, the first electrode 42 may have poor surface planarization. Therefore, bumps or peaks may be easily formed on the surface, and the organic electroluminescent device may not have normal operation due to leakage current from the bumps or the peaks. Accordingly, the number of pixels that do not emit light increases as using time passes, and the lifetime of the device may be shortened.
In addition, if the second passivation layer 46 is made of an inorganic material, to form the opening 44, the second passivation layer 46 may be etched through a dry etching process using a gas mixture of SF6 and O2 or CF4 and O2. At this time, if the first electrode 42 is made of indium-tin-oxide (ITO), which is a transparent conducting material, it is not easy to control the Fermi level of the first electrode 42 as expected because of the gas mixture.